The invention relates to semiconductor integrated circuit memory devices and, in particular, to an electrically erasable programmable read only memory (EEPROM) transistor.
EEPROM devices employ a floating gate that is a conductive electrode, insulated from other electrodes, used to store electrical charge indicative of the state of the device. The manner of reading the charge on the floating gate is well-known. For example, when charge is present on the floating gate, the device may indicate a binary zero and when charge is not present on the floating gate, a binary one is indicated. Charge is applied to the floating gate by a phenomenon known as Fowler-Nordheim tunneling, or more recently, by band-to-band tunneling. The floating gate was spaced above and separated from the substrate by a layer of thin oxide, having a thickness in the range of 40 or fewer Angstroms to about 70 Angstroms. Since this oxide is applied as a horizontal layer, there is no alignment or deposition problem. In a memory array, millions of identical memory devices are aligned in rows and columns for data storage. Each cell must be an efficient charge storage device. As devices become smaller, it becomes more difficult to maintain charge storage, leading to data retention integrity issues.
In U.S. Pat. No. 5,618,742 to F. Shone et al. a flash EPROM is shown wherein a main floating gate poly body is used for self-aligned placement of source and drain regions. Lateral poly spacers contact the main poly body to form an extended floating gate. U.S. Pat. No. 6,043,530 to M. B. Chiang, U.S. Pat. No. 6,074,914 to S. Ogura, and U.S. Pat. No. 6,124,170 to M. Lim et al. also show lateral poly spacers.
In U.S. Pat. No. 6,479,351, entitled xe2x80x9cMethod of Fabricating a Self-Aligned Non-Volatile Memory Cellxe2x80x9d, assigned to the assignee of the present invention, B. Lojek discloses a self-aligned non-volatile memory cell behaving like an EEPROM with a small, upright, conductive sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate and both form the floating gate of the non-volatile memory cell. Both are isolated electrically from the substrate by an oxide layer that is thinner between the small sidewall spacer and the substrate; and is thicker between the main floating gate region and the substrate.
The sidewall spacer has an adjacent thin oxide layer separating it from the main floating region creating a thin dielectric pathway for electrons to tunnel into either the spacer or the main polysilicon floating gate region, both forming the floating gate electrode. Part of the thin oxide layer is deposited vertically between the upright spacer and the main polysilicon body and part of the layer is deposited horizontally. Since the floating gate electrode is maintained at a single voltage indicating a single charge state, the multiple regions of the floating gate must be joined together by a conductive member in order to be at the same electrical potential. A layer of polysilicon applied after conductive spacer formation is usually used to join the floating spacers to the main polysilicon body. This multi-member floating gate construction is effective for providing multiple paths for tunneling through the thin oxide layer.
Separating the floating gate from the substrate is a layer of thin oxide, perhaps 30-60 Angstroms in thickness. As devices become smaller, the layer of thin oxide becomes more difficult to situate between the substrate and the floating gate. Also, the spacing and position of source and drain electrodes become more difficult to control.
An object of the invention is to provide an EEPROM device having an improved floating gate construction, with improved alignment of tunnel oxide and source and drain electrodes.
Another object of the invention is to provide a compact memory cell geometry with good charge storage and programming efficiency.
The above object has been met with a multi-member floating gate construction in a first active area wherein a self-alignment technique allows a uniform deposition of a thin, tunnel oxide layer in an EEPROM device that includes a vertical portion between the main floating gate body and adjacent conductive, upright conductive, sidewall spacers forming part of the floating gate. Prior to thin oxide deposition, the main floating gate body can be used as a mask for ion implantation of source and drain electrodes on opposite sides of the body. The ions are not driven deep, but just barely penetrate the substrate. The drain electrode is much larger than the source electrode, extending into an implanted region that reaches a nearby auxiliary active area, providing an unusually large charge reservoir for programming. The first active area and the auxiliary active area are adjacent, but insulated from each other. However, they share a large subsurface implanted or doped region which will serve as a reservoir for charged particles to be supplied to the floating gate. The entire footprint of the auxiliary active area is dedicated to this purpose.
A uniform thin oxide layer is deposited in a self aligned manner by first forming the main polysilicon body over an insulating layer of gate oxide and then etching back the gate oxide to the polysilicon body. It is very important that the tunnel oxide layer be both thin, preferably about 10 Angstroms, and uniform. This step is followed by vapor deposition of the thin tunnel oxide layer over the polysilicon body including its side walls. A subsequent layer of polysilicon is applied over the thin oxide layer and etched away, but not totally, leaving small corners of polysilicon adjacent to and against the main polysilicon body in a circumferential loop but separated therefrom by the previously deposited thin oxide. The residual polysilicon appears similar to nitride sidewall spacers, except that the newly formed spacers are conductive polysilicon spacers that are electrically joined to the main polysilicon body in a subsequent step.
The thin oxide between the poly spacers and the main polysilicon body allows electrons to have bidirectional tunneling opportunities, either into the main polysilicon body or into the poly spacers. This bi-directional tunneling opportunity increases the probability of electron transfers to and from the floating gate in charge transfer operations, such as write or erase operations, particularly using low voltages, and allows use of smaller polysilicon structures in forming the floating gate.
An insulative layer is deposited over the polysilicon members and later a conductive cap is deposited over the insulative layer joining multiple members of the floating gate. A hole formed through the cap is filled with metal, allowing joinder of the conductive cap to underlying floating gate members so that the main polysilicon body and the conductive spacers are at the same electrical potential. The extended drain structure, cooperating with the multi-element floating gate structure leads to a compact memory cell geometry with good charge storage and programming efficiency.